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T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES
* Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces * Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces * Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interfaces * Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface * Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz * Accepts two independent reference inputs which may have same or different nominal frequencies applied to them * Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o output clock signals * Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o, F32o, RSP and TSP
PRELIMINARY IDT82V3012
* Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 * Holdover frequency accuracy of 0.00625 ppm * Phase slope of 5 ns per 125 s * Attenuates wander from 2.1 Hz * Fast lock mode * Provides Time Interval Error (TIE) correction * MTIE of 600 ns * JTAG boundary scan * Holdover status indication * Freerun status indication * Normal status indication * Lock status indication * Input reference quality indication * 3.3 V operation with 5 V tolerant I/O * Package available: 56-pin SSOP
FUNCTIONAL BLOCK DIAGRAM
TDO TDI OSCi TCLR RST VDD VSS VDD VSS VDD VSS VDD VSS C2/C1.5 TCK TMS TRST Fref0 Fref1 IN_sel FLOCK DPLL JTAG OSC C32o C19o C19POS C19NEG TIE Control Block
Virtual Reference
Reference Input Switch
C16o C8o C4o C2o C3o C1.5o C6o F0o F8o F16o F19o F32o RSP TSP LOCK
Frequency Select Circuit 0
MON_out0
Reference Input Monitor 0 Reference Input Monitor 1
Feedback Signal
MON_out1
Invalid Input Signal Detection
F0_sel0 F0_sel1
State Control Circuit
Frequency Select Circuit 1
F1_sel0 F1_sel1
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc.
JULY 21, 2003
DSC-6238/2
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The IDT82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The IDT82V3012 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/ wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The IDT82V3012 can be used in synchronization and timing control for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse source. It also can be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
MODE_sel0 MODE_sel1 TCLR RST Fref0 Fref1 MON_out0 MON_out1 F0_sel0 F0_sel1 IN_sel VSS VDD C6o C1.5o C3o C2o VSS VDD C4o C19POS C19NEG C8o C16o C32o VDD VSS TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 TIE_en IC2 C2/C1.5 IC0 HOLDOVER FREERUN OSCi F19o VDD VSS NORMAL FLOCK LOCK C19o TSP RSP F32o F16o VSS VDD F8o F1_sel0 F1_sel1 F0o TDI TMS TRST TDO
IDT82V3012
Figure - 1 IDT82V3012 SSOP56 Package Pin Assignment
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
TABLE OF CONTENTS
1 2 Pin Description...................................................................................................................................................................................................7 Functional Description ......................................................................................................................................................................................9 2.1 State Control Circuit ..................................................................................................................................................................................9 2.1.1 Normal Mode..............................................................................................................................................................................10 2.1.2 Fast Lock Mode..........................................................................................................................................................................10 2.1.3 Holdover Mode ...........................................................................................................................................................................10 2.1.4 Freerun Mode.............................................................................................................................................................................10 2.2 Frequency Select Circuit .........................................................................................................................................................................10 2.3 Reference Input Switch ...........................................................................................................................................................................10 2.4 Reference Input Monitor ..........................................................................................................................................................................11 2.5 Invalid Input Signal Detection ..................................................................................................................................................................11 2.6 TIE Control Block.....................................................................................................................................................................................11 2.7 DPLL Block..............................................................................................................................................................................................12 2.7.1 Phase Detector (PHD)................................................................................................................................................................12 2.7.2 Limiter.........................................................................................................................................................................................12 2.7.3 Loop Filter ..................................................................................................................................................................................13 2.7.4 Fraction Block.............................................................................................................................................................................13 2.7.5 Digital Control Oscillator (DCO)..................................................................................................................................................13 2.7.6 Lock Indicator .............................................................................................................................................................................13 2.7.7 Output Interface..........................................................................................................................................................................13 2.8 OSC.........................................................................................................................................................................................................14 2.8.1 Clock Oscillator ..........................................................................................................................................................................14 2.9 JTAG .......................................................................................................................................................................................................14 2.10 Reset Circuit ............................................................................................................................................................................................14 Measures of Performance ...............................................................................................................................................................................15 3.1 Intrinsic Jitter ...........................................................................................................................................................................................15 3.2 Jitter Tolerance........................................................................................................................................................................................15 3.3 Jitter Transfer ..........................................................................................................................................................................................15 3.4 Frequency Accuracy................................................................................................................................................................................15 3.5 Holdover Accuracy ..................................................................................................................................................................................15 3.6 Capture Range ........................................................................................................................................................................................15 3.7 Lock Range .............................................................................................................................................................................................15 3.8 Phase Slope ............................................................................................................................................................................................15 3.9 Time Interval Error (TIE)..........................................................................................................................................................................15 3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................15 3.11 Phase Continuity .....................................................................................................................................................................................16 3.12 Phase Lock Time.....................................................................................................................................................................................16 Absolute Maximum Ratings ............................................................................................................................................................................17 Recommended DC Operating Conditions .....................................................................................................................................................17 DC Electrical Characteristics ..........................................................................................................................................................................17 6.1 Single End Input/Output Port...................................................................................................................................................................17 6.2 Differential Output Port (LVDS) ...............................................................................................................................................................18 AC Electrical Characteristics .........................................................................................................................................................................19 7.1 Performance ............................................................................................................................................................................................19 7.2 Intrinsic Jitter Unfiltered ...........................................................................................................................................................................20 7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................20 7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................20 7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................20 7.6 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21 7.7 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................21 7.8 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................21 7.9 19.44 MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................22
3
3
4 5 6
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7.10 7.11 7.12 7.13 8
8 kHz Input Jitter Tolerance.....................................................................................................................................................................22 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................22 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................23 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................23
Timing Characteristics ....................................................................................................................................................................................25 8.1 Timing Parameter Measurement Voltage Levels ....................................................................................................................................25 8.2 Input/Output Timing .................................................................................................................................................................................25 Ordering Information .......................................................................................................................................................................................30
9
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
LIST OF FIGURES
Figure - 1 Figure - 2 Figure - 3 Figure - 4 Figure - 5 Figure - 6 Figure - 7 Figure - 8 Figure - 9 Figure - 10 Figure - 11 Figure - 12 Figure - 13 Figure - 14 IDT82V3012 SSOP56 Package Pin Assignment ................................................................................................................................ 2 State Control Circuit ............................................................................................................................................................................ 9 State Control Diagram......................................................................................................................................................................... 9 TIE Control Block Diagram................................................................................................................................................................ 11 Reference Switch with TIE Control Block Enabled............................................................................................................................ 12 Reference Switch with TIE Control Block Disabled........................................................................................................................... 12 DPLL Block Diagram ......................................................................................................................................................................... 13 Clock Oscillator Circuit ...................................................................................................................................................................... 14 Power-Up Reset Circuit..................................................................................................................................................................... 14 Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25 Input to Output Timing (Normal Mode).............................................................................................................................................. 27 Output Timing 1................................................................................................................................................................................. 28 Output Timing 2................................................................................................................................................................................. 29 Input Control Setup and Hold Timing ................................................................................................................................................ 29
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
LIST OF TABLES
Table - 1 Table - 2 Table - 3 Table - 4 Table - 5 Operating Modes Selection ..................................................................................................................................................................9 Fref0 Frequency Selection .................................................................................................................................................................10 Fref1 Frequency Selection .................................................................................................................................................................10 Input Reference Selection ..................................................................................................................................................................11 C2/C1.5 Output Frequency Control....................................................................................................................................................14
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
1
Name VSS VDD OSCi
PIN DESCRIPTION
Type Power Power (CMOS) I Pin Number 12, 18, 27 38, 47 13, 19, 26 37, 48 50 Description Ground. 0 V. All VSS pins should be connected to the ground. Positive Supply Voltage. All VDD pins should be connected to +3.3 V (nominal). Oscillator Master Clock Input. This pin is connected to a clock source. Reference Input 0 and Reference Input 1. These are two input reference sources (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44 MHz) used for synchronization. The IN_sel pin determines which one of the two reference inputs to be used. See Table - 4 for details. The frequency of the reference inputs can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. These two pins are internally pulled up to VDD. Input Reference Selection. A logic low at this pin selects Reference Input 0 (Fref0) and a logic high at this pin selects Reference Input 1 (Fref1). The logic level on this input is gated in by the rising edges of F8o. This Pin is internally pulled down to VSS. Frequency Selection Inputs for Fref0. These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the Reference Input 0 (Fref0). See Table - 2 for details. Frequency Selection Inputs for Fref1. These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the Reference Input 1 (Fref1). These two pins are internally pulled down to Vss. See Table - 3 for details. Mode Selection Inputs. These two inputs determine the operating mode of the IDT82V3012 (Normal, Holdover or Freerun). See Table - 1 for details. The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down to VSS. Reset Input. Pulling this pin to logic low for at least 300 ns will reset the IDT82V3012. While the RST pin is low, all framing and clock outputs are at logic high. To ensure proper operation, the device must be reset after it is powered up. TIE Control Block Reset. Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and result in a realignment of the output phase with the input phase. This pin is internally pulled up to VDD. TIE Control Block Enable. A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this input is gated in by the rising edges of F8o. This pin is internally pulled down to Vss. Fast Lock Mode Enable. When this pin is set to logic high, the DPLL will quickly lock to the input reference within 500 ms. Lock Indicator. This output pin will go high when the DPLL is frequency locked to the input reference. Holdover Indicator. This output pin will go high whenever the DPLL enters Holdover mode. Normal Indicator. This output pin will go high whenever the DPLL enters Normal mode. Freerun Indicator. This output pin will go high whenever the DPLL enters Freerun mode. Frequency Out-of-range Indicator for Fref0. A logic high at this pin indicates that Fref0 is off the nominal frequency by more than 12 ppm. Frequency Out-of-range Indicator for Fref1. A logic high at this pin indicates that Fref1 is off the nominal frequency by more than 12 ppm. 19.44 MHz Clock Output (LVDS Level). This pair of outputs is used for OC3/STS3 applications. 19.44 MHz Clock Output (CMOS Level). This output is used for OC3/STS3 applications. 7
Fref0 Fref1
I
5 6
IN_sel F0_sel0 F0_sel1 F1_sel0 F1_sel1
I
11 9 10 35 34
I
I
MODE_sel0 MODE_sel1
I
1 2
RST
I
4
TCLR
I
3
TIE_en FLOCK LOCK HOLDOVER NORMAL FREERUN MON_out0 MON_out1 C19POS C19NEG C19o
I I (CMOS) O (CMOS) O (CMOS) O (CMOS) O O O (LVDS) O (CMOS) O
56 45 44 52 46 51 7 8 21 22 43
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS Name C32o C16o C8o C4o C2o C3o C1.5o C6o Type (CMOS) O (CMOS) O (CMOS) O (CMOS) O (CMOS) O (CMOS) O (CMOS) O (CMOS) O Pin Number 25 24 23 20 17 16 15 14 Description
INDUSTRIAL TEMPERATURE RANGE
C2/C1.5
(CMOS) O
54
F19o F32o
(CMOS) O (CMOS) O
49 40
F16o F8o F0o
(CMOS) O (CMOS) O (CMOS) O
39 36 33
RSP
(CMOS) O
41
TSP
(CMOS) O
42
TDO TDI TRST TCK TMS IC0, IC2
(CMOS) O I I I I -
29 32 30 28 31 53, 55
32.768 MHz Clock Output. This output is a 32.768 MHz clock used for ST-BUS operation. 16.384 MHz Clock Output. This output is a 16.384 MHz clock used for ST-BUS operation. 8.192 MHz Clock Output. This output is an 8.192 MHz clock used for ST-BUS operation. 4.096 MHz Clock Output. This output is a 4.096 MHz clock used for ST-BUS operation. 2.048 MHz Clock Output. This output is a 2.048 MHz clock used for ST-BUS operation. 3.088 MHz Clock Output. This output is used for T1 applications. 1.544 MHz Clock Output. This output is used for T1 applications. 6.312 MHz Clock Output. This output is used for DS2 applications. 2.048 MHz or 1.544 MHz Clock Output. This output is a 2.048 MHz or 1.544 MHz clock signal. If the selected reference input (Fref0 or Fref1) is 8 kHz, 2.048 MHz, or 19.44 MHz, the C2/C1.5 pin will output a 2.048 MHz clock signal. If the frequency of the selected reference input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock signal. Refer to Table - 5 for details. 8 kHz Frame Signal with 19.44 MHz Pulse Width. This output is used for OC3/STS3 applications. Frame Pulse ST-BUS 8.192 Mb/s. This is an 8 kHz 30 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal is typically used for ST-BUS operation at 8.192 Mb/s. Frame Pulse ST-BUS 8.192 Mb/s. This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal is typically used for ST-BUS operation at 8.192 Mb/s. Frame Pulse. This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame. Frame Pulse ST-BUS 2.048 Mb/s. This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal is typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s. Receive Sync Pulse. This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of a ST-BUS frame. This framing signal is typically used to connect to the Siemens MUNICH-32 device. Transmit Sync Pulse. This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This framing is typically used to connect to the Siemens MUNICH-32 device. Test Serial Data Out. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Serial Data In. JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. Test Reset. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally pulled up to VDD. It is connected to the ground for normal applications. Test Clock. Provides the clock for the JTAG test logic. Test Mode Select. JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. These pins should be connected to VSS.
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IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
TIE Block Enable/Disable DPLL Block Mode Control
2
FUNCTIONAL DESCRIPTION
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs, providing timing (clock) and synchronization (framing) signals to interface circuits for multitrunk T1/E1 and STS3/OC3 links. The details are described in the following sections.
Output of the Invalid Input Signal Detection IN_sel
State Control Circuit
TIE_en MODE_sel1 MODE_sel0
F8o
2.1
STATE CONTROL CIRCUIT
The State Control Circuit is an important part in the IDT82V3012. It is used to control the TIE block and the DPLL block as shown in Figure - 2. The control is based on the result of Invalid Input Signal Detection and the logic levels on the MODE_sel0, MODE_sel1, IN_sel and TIE_en pins. The IDT82V3012 can be operated in three different modes: Normal, Holdover and Freerun. The operating mode is selected by the MODE_sel1 and MODE_sel0 pins, as shown in Table - 1. Figure - 3 shows the state control diagram. All state changes occur synchronously on the rising edge of F8o. Three operating modes, Normal (S1), Holdover (S3) and Freerun (S0) can be switched from one to another by changing the logic levels on the MODE_sel0 and MODE_sel1 pins.
Figure - 2 State Control Circuit Table - 1 Operating Modes Selection
Mode Selection Pins MODE_sel1 MODE_sel0 Operating Mode
0 0 1 1
Reset *
0 1 0 1
Normal Holdover Freerun Reserved
o Aut
e abl Dis TIE IE oT Aut
e abl Dis
S0 Freerun Mode_sel1 = 1 Mode_sel0 = 0
Auto
Aut oTI E
TIE Disa ble
Dis abl e
(Valid Input Reference Signal) TIE Enable (TIE_en = H) (Valid Input Reference Signal) TIE Disable (TIE_en = L) (Invalid Input Reference Signal) Auto TIE Disable
Aut oTI E
S1 Normal Mode_sel1 = 0 Mode_sel0 = 0
S2 Auto - Holdover Mode_sel1 = 0 Mode_sel0 = 0
TI E
TIE E
Dis
nab le (
ab le
(TI E
TIE _en =
Dis abl e H)
to Au
ble isa ED TI
_e n=
L)
S3 Holdover Mode_sel1 = 0 Mode_sel0 = 1
nt s ie an Tr le el ab _s IN Dis TIE
to Au
D TIE
No IN
t sien Tran _sel ) n=L IE_e le (T isab
No IN_ sel TIE Tra En nsi abl ent e (T IE_ en =H )
S4 Short Time Holdover Mode_sel1 = 0 Mode_sel0 = 0
t sien Tran _sel IN ble Disa TIE Auto
* Note: After reset, the Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.
Figure - 3 State Control Diagram
9
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
The mode changes between Normal (S1) and Auto-Holdover (S2) are triggered by the Invalid Input Reference Detection Circuit and are irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At the stage of S1, if the input reference is invalid (out of the capture range), the operating mode will be changed to Auto-Holdover (S2) automatically. At the stage of S2, if no IN_sel transient occurs and the input reference becomes valid, the operating mode will be changed back to Normal (S1) automatically. If an IN_sel transient is detected at the stage of S2, the operating mode will be changed to Short Time Holdover (S4) with the TIE Control Block automatically disabled. Refer to "2.5 Invalid Input Signal Detection" for more information. The mode changes between Normal (S1) and Short Time Holdover (S4) are triggered by the IN_sel transient. At the stage of S1, if a voltage transient occurs on the IN_sel pin, the operating mode will be changed to Short Time Holdover (S4) automatically. At the stage of S4, if no voltage transient occurs on the IN_sel pin, the operating mode will be changed back to S1 automatically. See "2.3 Reference Input Switch" for details. When changing the operating mode, the TIE control block is enabled/ disabled automatically by the state control circuit as shown in Figure - 3, except for the changes from Normal (S1) to Auto-Holdover (S2), and from Auto-Holdover (S2), Holdover (S3) and Short Time Holdover (S4) to Normal (S1). During these four changes, the TIE control block can be enabled or disabled, depending on the logic level on the TIE_en pin. 2.1.1 NORMAL MODE
which corresponds to a worst case of 18 frame (125 s per frame) slips in 24 hours. This meets the AT&T TR62411 and Telcordia GR-1244CORE Stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours). Whenever the IDT82V3012 works in the Holdover mode, the HOLDOVER pin will be set to logic high. 2.1.4 FREERUN MODE
The Freerun mode is typically used when a master clock source is required, or used when a system is just powered up and the network synchronization has not been achieved. In this mode, the IDT82V3012 provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the input reference signal. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32 ppm output clock is required, the master clock must also be 32 ppm. Refer to "2.8 OSC" for more information. Whenever the IDT82V3012 works in the Freerun mode, the FREERUN pin will be set to logic high.
2.2
FREQUENCY SELECT CIRCUIT
The Normal mode is typically used when a slave clock source synchronized to the network is required. In this mode, the IDT82V3012 provides timing (C1.5o, C3o, C2o, C4o, C8o, C16o, C19o, C32o) and synchronization (F0o, F8o, F16o, F19o, F32o, TSP, RSP) signals. All these signals are synchronous to one of the two input references. The nominal frequency of the input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. After reset, the IDT82V3012 will take 30 seconds at most to make the output signals synchronous (phase locked) to the input reference. Whenever the IDT82V3012 works in the Normal mode, the NORMAL pin will be set to logic high. 2.1.2 FAST LOCK MODE
The input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. The F0_sel1 and F0_sel0 pins select one of the four frequencies for the reference input 0 (Fref0). The F1_sel1 and F1_sel0 pins select one of the four frequencies for the reference input 1 (Fref1). See Table 2 and Table - 3 for details. The reference inputs Fref0 and Fref1 may have different frequencies applied to them. Every time the frequency is changed, the device must be reset to make the change effective. Table - 2 Fref0 Frequency Selection
Frequency Selection Pins F0_sel1 F0_sel0 Fref0 Input Frequency
0 0 1 1
0 1 0 1
19.44 MHz 8 kHz 1.544 MHz 2.048 MHz
The Fast Lock mode is a submode of the Normal mode. It allows the DPLL to lock to a reference more quickly than the Normal mode allows. Typically, the locking time in the Fast Lock mode is less than 500 ms. When the FLOCK pin is set to high, the Fast Lock mode will be enabled. 2.1.3 HOLDOVER MODE
Table - 3 Fref1 Frequency Selection
Frequency Selection Pins F1_sel1 F1_sel0 Fref1 Input Frequency
The Holdover mode is typically used for short duration (e.g., 2 seconds) while network synchronization is temporarily disrupted. In the Holdover mode, the IDT82V3012 provides timing and synchronization signals that are not locked to an external reference signal, but are based on storage techniques. In the Normal mode, when the output frequency is locked to the input reference signal, a numerical value corresponding to the output frequency is stored alternately in two memory locations every 30 ms. When the device is changed to the Holdover mode, the stored value from between 30 ms and 60 ms is used to set the output frequency of the device. The frequency accuracy in the Holdover mode is 0.00625 ppm,
10
0 0 1 1
0 1 0 1
19.44 MHz 8 kHz 1.544 MHz 2.048 MHz
2.3
REFERENCE INPUT SWITCH
The IDT82V3012 accepts two simultaneous reference signals Fref0 and Fref1, and operates on the falling edge (8 kHZ, 1.544 MHz and
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
2.048 MHz) or rising edge (19.44 MHz). One of the two reference signals will be input to the device, as determined by the IN_sel pin. See Table - 4. The selected reference signal is sent to the TIE control block, Reference Input Monitor and Invalid Input Signal Detection block for further processing. Table - 4 Input Reference Selection
IN_sel Input Reference
MON_out1 signals are updated every 2 seconds.
2.5
INVALID INPUT SIGNAL DETECTION
0 1
Fref0 Fref1
When a transient voltage occurs on the IN_sel pin, the operating mode will be changed to Short Time Holdover (S4) with the TIE Control Block automatically disabled. At the stage of S4, if no IN_sel transient occurs, the reference signal will be switched from one to the other, and the operating mode will be changed back to Normal (S1) automatically. During the change from S4 to S1, the TIE Control Block can be enabled or disabled, depending on the logic level on the TIE_en pin. See Figure 3 for details.
This circuit is used to detect if the selected input reference (Fref0 or Fref1) is out of the capture range. Refer to "3.6 Capture Range" for details. This includes a complete loss of the input reference and a large frequency shift in the input reference. If the input reference is invalid (out of the capture range), the IDT82V3012 will be automatically changed to the Holdover mode (AutoHoldover). When the input reference becomes valid, the device will be changed back to the Normal mode and the output signals will be locked to the input reference. In the Holdover mode, the output signals are based on the output reference signal 30 ms to 60 ms prior to entering the Holdover mode. The amount of phase drift while in holdover can be negligible because the Holdover mode is very accurate (e.g., 0.00625 ppm). Consequently, the phase delay between the input and output after switching back to the Normal mode is preserved.
2.4
REFERENCE INPUT MONITOR
2.6
TIE CONTROL BLOCK
The Telcordia GR-1244-CORE standard recommends that the DPLL should be able to reject the references that are off the nominal frequency by more than 12 ppm. The IDT82V3012 monitors the Fref0 and Fref1 frequencies and outputs two signals at MON_out0 pin and MON_out1 pin to indicate the monitoring results respectively. Whenever the Fref0 frequency is off the nominal frequency by more than 12 ppm, the MON_out0 pin will go high. The MON_out1 pin indicates the monitoring result of Fref1 in the same way. The MON_out0 and
TIE_en
If the current reference is badly damaged or lost, it is necessary to use the other reference or the one generated by storage techniques instead. But when switching the reference, a step change in phase on the input reference will occur. A step change in phase in the input to DPLL may lead to an unacceptable phase change on the output signals. The TIE control block, when enabled, prevents a step change in phase on the input reference signals from causing a step change in phase on the output of the DPLL block. Figure - 4 shows the TIE Control Block diagram.
Step Generation
IN_sel Fref0 Fref1 Feedback Signal Reference Select Circuit Fref Measure Circuit Storage Circuit Trigger Circuit Virtual Reference Signal
TCLR
Figure - 4 TIE Control Block Diagram When the TIE Control Block is enabled manually or automatically (by the TIE_en pin or TIE auto-enable logic generated by the State Control Circuit), it works under the control of the Step Generation circuit. At the Measure Circuit stage, the selected reference signal (Fref0 or Fref1) is compared with the feedback signal (current output feed back from the Frequency Select Circuit). The phase difference between the input reference and the feedback signal is stored in the Storage Circuit for TIE correction. According to the value stored in the storage circuit, the Trigger Circuit generates a virtual reference with the same phase as the previous reference. In this way, the reference can be switched without generating a step change in phase. Figure - 5 shows the phase transient that will result if a reference switch is performed with the TIE Control Block enabled. The value of the phase difference in the Storage Circuit can be
11
cleared by applying a logic low reset signal to the TCLR pin. The minimum width of the reset pulse should be 300 ns. When the IDT82V3012 primarily enters the Holdover mode for a short time period and then returns back to the Normal mode, the TIE Control Circuit should not be enabled. This will prevent undesired accumulated phase change between the input and output. If the TIE Control Block is disabled manually or automatically, a reference switch will result in a phase alignment between the input signal and the output signal as shown in Figure - 6. The slope of the phase adjustment is limited to 5 ns per 125 s.
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s
Input Clock
Output Clock
Figure - 5 Reference Switch with TIE Control Block Enabled
Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s
Input Clock
Output Clock
Figure - 6 Reference Switch with TIE Control Block Disabled
2.7
DPLL BLOCK
As shown in Figure - 7, the DPLL Block consists of a Phase Detector, a Limiter, a Loop Filter, a Digital Control Oscillator and Divider. 2.7.1 PHASE DETECTOR (PHD)
In the Freerun or Holdover mode, the Frequency Select Circuit, the Phase Detector and the Limiter are inactive, and the input reference signal is not used. 2.7.2 LIMITER
In the Normal mode, the Phase Detector compares the virtual reference signal from the TIE Control Circuit with the feedback signal from the Frequency Select Circuit, and outputs an error signal corresponding to the phase difference. This error signal is sent to the Limiter circuit for phase slope control.
12
The Limiter is used to limit the phase slope. It ensures that the maximum output phase slope is limited to 5 ns per 125 s for all input transient conditions. This well meets the AT&T TR62411 and Telcordia GR-1244-CORE specifications, which specify the maximum phase slope of 7.6 ns per 125 s and 81 ns per 1.326 ms respectively.
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
Fx_sel1 Fx_sel0 (x = 0 or 1)
Output Interface
C2/C1.5 C19POS C19NEG C19o F19o
Fraction_C19
19.44 MHz
APLL
155.52 MHz
C19_Divider
Digital Control Oscillator
Fraction_T1
24.704 MHz
T1_Divider
C1.5o C3o C2o C4o C8o C16o C32o
32.768 MHz
E1_Divider
F0o F8o F16o F32o RSP TSP
Fraction_C6
25.248 MHz
C6_Divider
C6o
Loop Filter
Limiter
Phase Detector
Feedback Signal
Frequency Selection Circuit 1
IN_sel F1_sel1 F1_sel0
Frequency Selection Circuit 0
F0_sel1 F0_sel0
FLOCK
Virtual Reference
Figure - 7 DPLL Block Diagram In the Normal mode, the Limiter receives the error signal from the Phase Detector, limits the phase slope within 5 ns per 125 s and sends the limited signal to the Loop Filter. In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to the input reference within 500 ms, which is much shorter than that in the Normal mode. 2.7.3 LOOP FILTER 2.7.5 DIGITAL CONTROL OSCILLATOR (DCO)
The Loop Filter ensures that the jitter transfer meets the ETS 300 011 and AT&T TR62411 requirements. It works similarly to a first order low pass filter with 2.1 Hz cutoff frequency for the four valid input frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). The output of the Loop Filter goes to the Digital Control Oscillator directly or through the Fraction blocks, in which E1, T1, C6 and C19 signals are generated. 2.7.4 FRACTION BLOCK
In the Normal mode, the DCO receives four limited and filtered signals from Loop Filter or Fraction blocks. Based on the values of the received signals, the DCO generates four digital outputs: 19.44 MHz, 25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1 dividers respectively. In the Holdover mode, the DCO is running at the same frequency as that generated by storage techniques. In the Freerun mode, the DCO is running at the same frequency as that of the master clock. 2.7.6 LOCK INDICATOR
If the output frequency of the DPLL is identical to the input frequency, and the input phase offset is small enough so that no slope limiting is exhibited, the LOCK pin will be set high. 2.7.7 OUTPUT INTERFACE
By applying some algorithms to the incoming E1 signal, the Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6 and T1 signals respectively.
13
The Output Interface uses three output signals from the DCO to generate totally 9 types of clock signals and 7 types of framing signals All these output signals are synchronous to F8o.
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
The 32.768 MHz signal is used by the E1_divider to generate five types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal 50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o, RSP and TSP). The 24.704 MHz signal is used by the T1_divider to generate two types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle. The 25.248 MHz signal is used by the C6_divider to generate a C6o signal with nominal 50% duty cycle. The 19.44 MHz signal is sent to an APLL, which outputs a 155.52 MHz signal. The 155.52 MHz signal is used by the C19_divider to generate 19.44 MHz clock signals (C19o, C19POS and C19NEG) with nominal 50% duty cycle and a framing signal F19o. Additionally, the IDT82V3012 provides an output clock (C2/C1.5) with the frequency controlled by the frequency selection pins Fx_sel0 and Fx_sel1 (see Table - 5 for details). If the selected reference input (Fref0 or Fref1) is 8 kHz, 2.048 MHz or 19.44 MHz, the C2/C1.5 pin will output a 2.048 MHz clock signal. If the selected reference input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock signal. The electrical and timing characteristics of this output (2.048 MHz or 1.544 MHz) is the same as that of C2o or C1.5o. Table - 5 C2/C1.5 Output Frequency Control
Frequency Selection Pins Fx_sel1 Fx_sel0 Frefx Input Frequency C2/C1.5 Output Frequency
For applications requiring 32 ppm clock accuracy, the following clock oscillator module may be used. FOX F7C-2E3-20.0 MHz Frequency: 20.0 MHz Tolerance: 25 ppm 0C to 70C Rise & Fall Time: 10 ns (0.33 V, 2.97 V, 15 pF) Duty Cycle: 40% to 60% For Stratum 3 application, the clock oscillator should meet the following requirements: Frequency: 20.0 MHz Tolerance: 4.6 ppm over 20 years life time Drift: 0.04 ppm per day @ constant temperature 0.3 ppm over temperature range of 0 to 70C The output clock should be connected directly (not AC coupled) to the OSCi input of the IDT82V3012, as shown in Figure - 8.
IDT82V3012
+3.3 V
OSCi
+3.3 V 20 MHz OUT GND
0.1 F
0 0 1 1
0 1 0 1
19.44 MHz 8 kHz 1.544 MHz 2.048 MHz
2.048 MHz 2.048 MHz 1.544 MHz 2.048 MHz Figure - 8 Clock Oscillator Circuit
Note: `x' can be 0 or 1, as selected by IN_sel pin. IN_sel = 0: x = 0, Fref0 is the selected reference input. The frequency of Fref0 is determined by F0_sel0 and F0_sel1 pins. IN_sel = 1: x = 1, Fref1 is the selected reference input. The frequency of Fref1 is determined by F1_sel0 and F1_sel1 pins.
2.9
JTAG
The IDT82V3012 supports IEEE 1149.1 JTAG Scan.
2.10
RESET CIRCUIT
2.8
OSC
The IDT82V3012 can use a clock as the master timing source. In the Freerun mode, the frequency tolerance of the clock outputs is identical to that of the source at the OSCi pin. For applications not requiring an accurate Freerun mode, the tolerance of the master timing source may be 100 ppm. For applications requiring an accurate Freerun mode, such as AT&T TR62411, the tolerance of the master timing source must be no greater than 32 ppm. The desired capture range should be taken into consideration when determining the accuracy of the master timing source. The sum of the accuracy of the master timing source and the capture range of the IDT82V3012 will always equal 230 ppm. For example, if the master timing source is 100 ppm, the capture range will be 130 ppm. 2.8.1 CLOCK OSCILLATOR
A simple power-up reset circuit is shown as Figure - 9. The logic low reset pulse is about 50 s. The resistor Rp is used for protection only and limits current into the RST pin during power down conditions. The logic low reset pulse width is not critical but should be greater than 300 ns.
IDT82V3012
R 10 k RST Rp 1 k C 1 F 3.3 V
When selecting a Clock Oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
Figure - 9 Power-Up Reset Circuit
14
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
3 MEASURES MANCE
OF
PERFOR-
accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
The following are some synchronizer performance indicators and their corresponding definitions.
3.4
FREQUENCY ACCURACY
3.1
INTRINSIC JITTER
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a nonsynchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. For the IDT82V3012, the intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and 1.544 MHz clocks.
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the IDT82V3012, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy.
3.5
HOLDOVER ACCURACY
3.2
JITTER TOLERANCE
Jitter tolerance is a measure of the ability of a DPLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards.
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the IDT82V3012, the storage value is determined while the device is in Normal mode and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the IDT82V3012 does not affect Holdover accuracy, but the change in OSCi accuracy while in Holdover mode does.
3.6
CAPTURE RANGE
3.3
JITTER TRANSFER
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the IDT82V3012, two internal elements determine the jitter attenuation. This includes the internal 2.1 Hz low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns per 125 s. Therefore, if the input signal exceeds this rate, such as for very large amplitude, low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5 ns per 125 s. The IDT82V3012 has 16 outputs with 4 possible input frequencies for a total of 39 possible jitter transfer functions. Since all outputs are derived from the same signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz, 2.048 MHz to 2.048 MHz and 19.44 MHz to 19.44 MHz can be applied to all outputs. It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds). Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the four jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz, 19.44 MHz) and outputs (8 kHz, 1.544 MHz, 3.088 MHz, 6.312 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 32.768 MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently,
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The IDT82V3012 capture range is equal to 230 ppm minus the accuracy of the master clock (OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm. The Telcordia GR-1244-CORE standard, recommends that the DPLL should be able to reject references that are off the nominal frequency by more than 12 ppm. The IDT82V3012 provides two pins, MON_out0 and MON_out1, to respectively indicate whether the reference inputs Fref0 and Fref1 are within 12 ppm of the nominal frequency.
3.7
LOCK RANGE
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the IDT82V3012.
3.8
PHASE SLOPE
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal.
3.9
TIME INTERVAL ERROR (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
3.10
MAXIMUM TIME INTERVAL ERROR (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period.
15
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
3.11
PHASE CONTINUITY
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the IDT82V3012, the output signal phase continuity is maintained to within 5 ns at the instance (over one frame) of all mode changes. The total phase shift, depending on the type of mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is limited to a maximum phase slope of approximately 5 ns per 125 s. This meets the AT&T TR62411 maximum phase slope requirement of 7.6 ns per 125 s and Telcordia GR-1244-CORE (81 ns per 1.326 ms).
3.12
PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors including: 1. Initial input to output phase difference 2. Initial input to output frequency difference 3. Synchronizer loop filter 4. Synchronizer limiter Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The IDT82V3012 loop filter and limiter are optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standard requirement, may be longer than in other applications. See "7.1 Performance"for details. The IDT82V3012 provides a FLOCK pin to enable the Fast Lock mode. When this pin is set to high, the DPLL will lock to an input reference within approximately 500 ms.
16
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
4
ABSOLUTE MAXIMUM RATINGS
Ratings Min.
-0.5 -0.5
Max.
5.0 5.5 200
Unit
V V mW
Power supply voltage Voltage on any pin with respect to ground Package power dissipation Storage temperature
-55
125
C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
5
RECOMMENDED DC OPERATING CONDITIONS
Parameter Min.
-40 3.0
Max.
+85 3.6
Unit
Operating temperature Power supply voltage
C
V
6
6.1
IDDS IDD VCIH VCIL VTIH VTIL
DC ELECTRICAL CHARACTERISTICS
SINGLE END INPUT/OUTPUT PORT
Description
Supply current with OSCi = 0 V Supply current with OSCi = Clock CMOS high-level input voltage CMOS low-level input voltage TTL high-level input voltage TTL low-level input voltage Input leakage current: Normal (low level) Normal (high level) Pull up (low level) Pull up (high level) Pull down (low level) Pull down (high level) High-level output voltage Low-level output voltage -15 -15 -100 -15 -15 0 2.4 0.4 2.0 0.8 15 15 0 15 15 100 0.7VDD 0.3VDD
Parameter
Min.
Typ.
Max.
10 60
Units
mA mA V V V V
Test Conditions *
Outputs unloaded Outputs unloaded OSCi, Fref0 and Fref1 OSCi, Fref0 and Fref1 All input pins except for OSCi, Fref0 and Fref1 All input pins except for OSCi, Fref0 and Fref1
IIL
A
VI = VDD or 0 V
VOH VOL
V V
IOH = 8 mA IOL = 8 mA
* Note: 1. Voltages are with respect to ground (VSS) unless otherwise stated. 2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
17
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
6.2
VOD
VOD
DIFFERENTIAL OUTPUT PORT (LVDS)
Description
Differential Output Voltage Change in Magnitude of VOD for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output Voltage High Output Voltage Low Output Rise time Output Fall time Output Short Circuit Current Differential Output Short Circuit Current 0.9 1.125
Parameter
Min.
250
Typ.
350 4 1.25 5 1.38 1.03 0.38 0.40 6.0 6.0
Max.
450 35 1.375 25 1.6
Units
mV mV V mV V V
Test Conditions
RL = 100 RL = 100 RL = 100 RL = 100 RL = 100 RL = 100 RL = 100 RL = 100
VOS
VOS
VOH VOL tTLH tTHL IOS IOSD
1.5 1.5 TBD 10
ns ns mA mA
18
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7
7.1
AC ELECTRICAL CHARACTERISTICS
PERFORMANCE
Description Min.
-0 -32 -100 -0.00625 -0.00625 -0.00625 -230 -198 -130 50 200 200 200 50 -12 -12 +12 +12 600 40 -18 k -36 k -36 k -36 k +18 k +36 k +36 k +36 k
Typ.
Max.
+0 +32 +100 +0.00625 +0.00625 +0.00625 +230 +198 +130
Units
ppm ppm ppm ppm ppm ppm ppm ppm ppm s ns ns ns ns ppm ppm ns s/s ppm ppm ppm ppm
Test Conditions / Notes (see "Notes" on page 24)
5-9 5-9 5-9 1, 2, 4, 6-9, 43, 44 1, 2, 4, 6-9, 43, 44 1, 2, 4, 6-9, 43, 44 1-3, 6-9 1-3, 6-9 1-3, 6-9 1-3, 6-15, 45 1-3, 6-15 1-2, 4-15 1-4, 6-15 1-3, 6-15
Freerun Mode accuracy with OSCi at: 0 ppm Freerun Mode accuracy with OSCi at: 32 ppm Freerun Mode accuracy with OSCi at: 100 ppm Holdover Mode accuracy with OSCi at: 0 ppm Holdover Mode accuracy with OSCi at: 32 ppm Holdover Mode accuracy with OSCi at: 100 ppm Capture range with OSCi at: 0 ppm Capture range with OSCi at: 32 ppm Capture range with OSCi at: 100 ppm Phase lock time Output phase continuity with reference switch Output phase continuity with mode switch to Normal Output phase continuity with mode switch to Freerun Output phase continuity with mode switch to Holdover Fref0 Frequency accuracy when MON_out0 is logic low Fref1 Frequency accuracy when MON_out1 is logic low MTIE (maximum time interval error) Output phase slope Reference input for Auto-Holdover with 8 kHz Reference input for Auto-Holdover with 1.544 MHz Reference input for Auto-Holdover with 2.048 MHz Reference input for Auto-Holdover with 19.44 MHz
1-15, 28 1-15, 28 1-3, 6, 10-12 1-3, 7, 10-12 1-3, 8, 10-12 1-3, 9, 10-12
19
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7.2
INTRINSIC JITTER UNFILTERED
Description Min. Typ. Max.
0.0001 0.0001 0.0001 0.015 0.03 0.01 0.06 0.02 0.04 0.04 0.0001 0.0001 0.08
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-15, 22-25, 29 1-15, 22-25, 29 1-15, 22-25, 29 1-15, 22-25, 30 1-15, 22-25, 32 1-15, 22-25, 31 1-15, 22-25, 34 1-15, 22-25, 33 1-15, 22-25, 35 1-15, 22-25, 36 1-15, 22-25, 29 1-15, 22-25, 29 1-15, 22-25, 38
Intrinsic jitter at F8o (8 kHz) Intrinsic jitter at F0o (8 kHz) Intrinsic jitter at F16o (8 kHz) Intrinsic jitter at C1.5o (1.544 MHz) Intrinsic jitter at C3o (3.088 MHz) Intrinsic jitter at C2o (2.048 MHz) Intrinsic jitter at C6o (6.312 MHz) Intrinsic jitter at C4o (4.096 MHz) Intrinsic jitter at C8o (8.192 MHz) Intrinsic jitter at C16o (16.834 MHz) Intrinsic jitter at TSP (8 kHz) Intrinsic jitter at RSP (8 kHz) Intrinsic jitter at C32o (32.768 MHz)
7.3
C1.5o (1.544 MHZ) INTRINSIC JITTER FILTERED
Description Min. Typ. Max.
0.008 0.006 0.006 0.003
Units
UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-15, 22-25, 30 1-15, 22-25, 30 1-15, 22-25, 30 1-15, 22-25, 30
Intrinsic jitter (4 Hz to 100 kHz filter) Intrinsic jitter (10 Hz to 40 kHz filter) Intrinsic jitter (8 kHz to 40 kHz filter) Intrinsic jitter (10 Hz to 8 kHz filter)
7.4
C2o (2.048 MHZ) INTRINSIC JITTER FILTERED
Description Min. Typ. Max.
0.005 0.004 0.003 0.002
Units
UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-15, 22-25, 31 1-15, 22-25, 31 1-15, 22-25, 31 1-15, 22-25, 31
Intrinsic jitter (4 Hz to 100 kHz filter) Intrinsic jitter (10 Hz to 40 kHz filter) Intrinsic jitter (8 kHz to 40 kHz filter) Intrinsic jitter (10 Hz to 8 kHz filter)
7.5
C19o (19.44 MHZ) INTRINSIC JITTER FILTERED
Description Min. Typ. Max.
2 0.5
Units
nspp nspp
Test Conditions / Notes (see "Notes" on page 24)
1-15, 22-25, 37 1-15, 22-25, 37
Intrinsic jitter (500 Hz to 1.3 MHz filter) Intrinsic jitter (65 kHz to 1.3 MHz filter)
20
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7.6
8 KHZ INPUT TO 8 KHZ OUTPUT JITTER TRANSFER
Description Min.
0 6 15 32 42 50
Typ.
Max.
6 16 22 38
Units
dB dB dB dB dB dB
Test Conditions / Notes (see "Notes" on page 24)
1-3, 6, 10-15, 22-23, 25, 29, 39 1-3, 6, 10-15, 22-23, 25, 29, 39 1-3, 6, 10-15, 22-23, 25, 29, 39 1-3, 6, 10-15, 22-23, 25, 29, 39 1-3, 6, 10-15, 22-23, 25, 29, 39 1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 1 Hz@0.01 UIpp input Jitter attenuation for 1 Hz@0.54 UIpp input Jitter attenuation for 10 Hz@0.10 UIpp input Jitter attenuation for 60 Hz@0.10 UIpp input Jitter attenuation for 300 Hz@0.10 UIpp input Jitter attenuation for 3600 Hz@0.005 UIpp input
7.7
1.544 MHZ INPUT TO 1.544 MHZ OUTPUT JITTER TRANSFER
Description Min.
0 6 17 33 45 48 50
Typ.
Max.
6 16 22 38
Units
dB dB dB dB dB dB dB
Test Conditions / Notes (see "Notes" on page 24)
1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39 1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 1 Hz@20 UIpp input Jitter attenuation for 1 Hz@104 UIpp input Jitter attenuation for 10 Hz@20 UIpp input Jitter attenuation for 60 Hz@20 UIpp input Jitter attenuation for 300 Hz@20 UIpp input Jitter attenuation for 10 kHz@0.3 UIpp input Jitter attenuation for 40 kHz@0.3 UIpp input
7.8
2.048 MHZ INPUT TO 2.048 MHZ OUTPUT JITTER TRANSFER
Description Min. Typ. Max.
2.5 0.07 1.4 0.10 0.90 0.10 0.40 0.10 0.06 0.05 0.04 0.03 0.04 0.02
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40 1-3, 8, 10-15, 22-23, 25, 31, 39 1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 1 Hz@3.00 UIpp input Jitter at output for 1 Hz@3.00 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 3 Hz@2.33 UIpp input Jitter at output for 3 Hz@2.33 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 5 Hz@2.07 UIpp input Jitter at output for 5 Hz@2.07 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 10 Hz@1.76 UIpp input Jitter at output for 10 Hz@1.76 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 100 Hz@1.50 UIpp input Jitter at output for 100 Hz@1.50 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 2400 Hz@1.50 UIpp input Jitter at output for 2400 Hz@1.50 UIpp input with 40 Hz to 100 kHz filter Jitter at output for 100 kHz@0.20 UIpp input Jitter at output for 100 kHz@0.20 UIpp input with 40 Hz to 100 kHz filter
21
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7.9
19.44 MHZ INPUT TO 19.44 MHZ OUTPUT JITTER TRANSFER
Description Min.
0 6 17 33 45 48 50
Typ.
Max.
6 16 22 38
Units
dB dB dB dB dB dB dB
Test Conditions / Notes (see "Notes" on page 24)
1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39 1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 1 Hz@20 UIpp input Jitter attenuation for 1 Hz@104 UIpp input Jitter attenuation for 10 Hz@20 UIpp input Jitter attenuation for 60 Hz@20 UIpp input Jitter attenuation for 300 Hz@20 UIpp input Jitter attenuation for 10 kHz@0.3 UIpp input Jitter attenuation for 40 kHz@0.3 UIpp input
7.10
8 KHZ INPUT JITTER TOLERANCE
Description Min.
0.80 0.70 0.60 0.16 0.14 0.07 0.02 0.01
Typ.
Max.
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29 1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input Jitter tolerance for 700 Hz input Jitter tolerance for 2400 Hz input Jitter tolerance for 3600 Hz input
7.11
1.544 MHZ INPUT JITTER TOLERANCE
Description Min.
150 140 130 38 25 15 5 1.2 0.5
Typ.
Max.
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30 1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input Jitter tolerance for 700 Hz input Jitter tolerance for 2400 Hz input Jitter tolerance for 10 kHz input Jitter tolerance for 40 kHz input
22
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
7.12
2.048 MHZ INPUT JITTER TOLERANCE
Description Min.
150 140 130 40 33 18 5.5 1.3 0.4
Typ.
Max.
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input Jitter tolerance for 700 Hz input Jitter tolerance for 2400 Hz input Jitter tolerance for 10 kHz input Jitter tolerance for 100 kHz input
7.13
19.44 MHZ INPUT JITTER TOLERANCE
Description Min.
2800 2800 311 311 39 39 1.5 1.5 0.15 0.15
Typ.
Max.
Units
UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Test Conditions / Notes (see "Notes" on page 24)
1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 12 Hz input Jitter tolerance for 178 Hz input Jitter tolerance for 0.0016 Hz input Jitter tolerance for 0.0156 Hz input Jitter tolerance for 0.125 Hz input Jitter tolerance for 19.3 Hz input Jitter tolerance for 500 Hz input Jitter tolerance for 6.5 kHz input Jitter tolerance for 65 kHz input Jitter tolerance for 1.3 MHz input
23
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Notes: Voltages are with respect to ground (VSS) unless otherwise stated. Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per Timing Parameter Measurement Voltage Levels. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. Fref0 reference input selected. Fref1 reference input selected. Normal mode selected. Holdover mode selected. Freerun mode selected. 8 kHz frequency mode selected. 1.544 MHz frequency mode selected. 2.048 MHz frequency mode selected. 19.44 MHz frequency mode selected. Master clock input OSCi at 20 MHz 0 ppm. Master clock input OSCi at 20 MHz 32 ppm. Master clock input OSCi at 20 MHz 100 ppm. Selected reference input at 0 ppm. Selected reference input at 32 ppm. Selected reference input at 100 ppm. For Freerun mode of 0 ppm. For Freerun mode of 32 ppm. For Freerun mode of 100 ppm. For capture range of 230 ppm. For capture range of 198 ppm. For capture range of 130 ppm.
INDUSTRIAL TEMPERATURE RANGE
22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45.
25 pF capacitive load. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz. Jitter on reference input is less than 7 nspp. Applied jitter is sinusoidal. Minimum applied input jitter magnitude to regain synchronization. Loss of synchronization is obtained at slightly higher input jitter amplitudes. Within 10 ms of the state, reference or input change. 1 UIpp = 125 s for 8 kHz signals. 1 UIpp = 648 ns for 1.544 MHz signals. 1 UIpp = 488 ns for 2.048 MHz signals. 1 UIpp = 323 ns for 3.088 MHz signals. 1 UIpp = 244 ns for 4.096 MHz signals. 1 UIpp = 158 ns for 6.312 MHz signals. 1 UIpp = 122 ns for 8.192 MHz signals. 1 UIpp = 61 ns for 16.484 MHz signals. 1 UIpp = 51 ns for 19.44 MHz signals. 1 UIpp = 30 ns for 32.968 MHz signals. No filter. 40 Hz to 100 kHz bandpass filter. With respect to reference input signal frequency. After a RST or TCLR. Master clock duty 40% to 60%. Prior to Holdover mode, device as in Normal mode and phase locked. With input frequency offset of 100 ppm.
24
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
8
8.1
TIMING CHARACTERISTICS
TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Parameter VT VHM VLM Description
Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low
CMOS
0.5VDD 0.7VDD 0.3VDD
Units
V V V
Timing Reference Points All Siganls
tIRF,tORF tIRF,tORF
VHM VT VLM
Figure - 10 Timing Parameter Measurement Voltage Levels
Notes: 1. Voltages are with respect to ground (VSS) unless otherwise stated. 2. Supply voltage and operating temperature are as per Recommended Operating Conditions. 3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2
Parameter tRW tIRF tR8D tR15D tR2D tR19D tFOD tF16S tF16H tF19S tF19H tC15D tC3D tC6D tC2D tC4D tC8D tC16D
INPUT/OUTPUT TIMING
Description
Reference input pulse width high or low Reference input rise or fall time 8 kHz reference input to F8o delay 1.544 MHz reference input to F8o delay 2.048 MHz reference input to F8o delay 19.44 MHz reference input to F8o delay F8o to F0o delay F16o setup to C16o falling F16o hold to C16o falling F19o setup to C19o falling F19o hold to C19o falling F8o to C1.5o delay F8o to C3o delay F8o to C6o delay F8o to C2o F8o to C4o F8o to C8o delay F8o to C16o delay -10 -10 -10 -11 -11 -11 -11 111 25 25 25 25 10 10 10 5 5 5 5 0 326 248 5 130 40 40
Min.
100 5
Typ.
Max.
Units
ns ns
Test Conditions
8 kHz, 1.544 MHz or 2.048 MHz reference input 19.44 MHz reference input
10 25 342 264
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
Parameter tC19D tC32D tTSPD tRSPD tC15W tC3W tC6W tC2W tC4W tC8W tC16W tC19W tC32W tTSPW tRSPW tF0WL tF8WH tF16WL tF19WH t0RF tS tH tF16D tF19D tF32D tF32S tF32H tF32WL
F8o to C19o delay F8o to C32o delay F8o to TSP delay F8o to RSP delay
Description
Min.
-11 -11 -6 -8 309 154 70 232 111 52 24
Typ.
Max.
5 5 10 8 339 169 86 258 133 70 35
Units
ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions
C1.5o pulse width high or low C3o pulse width high or low C6o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low C19o pulse width high or low C32o pulse width high or low TSP pulse width high RSP pulse width high F0o pulse width low F8o pulse width high F16o pulse width low F19o pulse width low Output clock and frame pulse rise or fall time Input controls setup Time Input controls hold Time F8o to F16o delay F8o to F19o delay F8o to F32o delay F32o setup to C32o falling F32o hold to C32o falling F32o pulse width low
25 14 478 474 234 109 47 25 9 100 100 24 25 12 11 11 15 31 19 38 16.78 494 491 254 135 72
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
26
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
Fref0/Fref1 8 kHz
tR8D tRW tR15D tRW
VT
Fref0/Fref1 1.544 MHz
VT
tR2D
Fref0/Fref1 2.048 MHz
tRW
VT
tRW tR19D
Fref0/Fref1 19.44 MHz F8o
VT VT
Figure - 11 Input to Output Timing (Normal Mode)
27
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
tF8WH F8o tF0W F0o
L
tF0D
VT VT
tF16WL F16o tF16S tF32WL F32o tC32W C32o tC16W C16o tC8W C8o tC4W C4o tC2W C2o
(see Note 1)
tF16D tF16H tF32D tF32H tC32D VT tC16D VT VT VT
tF32S
tC8W
tC8D VT
tC4W
tC4D tC2D
VT
VT tC6W tC3W tC6W tC6D VT tC3D tC15W tC15D VT tF19WH tF19S tC19W tF19D VT tF19H tC19D tC19D VT tC19W tC19D VT
Figure - 12 Output Timing 1
28
C6o C3o C1.5o
(see Note 1)
VT
F19o
C19o tC19W C19POS C19NEG
VT
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
F8o
VT
C2o tRSPD RSP tTSPW TSP tTSPD tRSPW
VT
VT
VT
Figure - 13 Output Timing 2
Note 1: The timing characteristic of C2/C1.5 (2.048 MHz or 1.544 MHz) is as same as that of C2o or C1.5o.
F8o
VT
MODE_sel0 MODE_sel1 TIE_en IN_sel
tS
tH VT
Figure - 14 Input Control Setup and Hold Timing
29
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
9
IDT
ORDERING INFORMATION
XXXXXXX Device Type XX Package X Process/ Temperature Range
Blank
Industrial (-40 C to +85 C)
PV
Shrink Small Outline Package (SSOP, PV56)
82V3012
T1/E1/OC3 WAN PLL with Dual Reference Inputs
DATASHEET DOCUMENT HISTORY
07/21/2003 pgs. 7, 8, 17.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
30
for Tech Support: email: telecomhelp@idt.com phone: 408-330-1753

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